Most digital electronic circuits operate in response to a clock signal. In some applications, a number of different integrated circuits (ICs) each require their own clock signal, with all the clock signals derived from and in phase with a reference clock.
One method of accomplishing this is with the use of a phase-locked loop (PLL) circuit, which receives a reference clock and produces an output signal which is in-phase with the reference clock. A conventional PLL circuit 100 is shown in FIG. 1. The PLL circuit 100 comprises a phase frequency detector (PFD) 102, a charge pump and loop filter 103, a voltage control oscillator (VCO) 105, a frequency divider 106 and a post divider 107. A reference clock signal (Refclk) 21 is applied to an input of the phase frequency detector 102, which also receives a divider signal 45 from the frequency divider 106. The PFD 102 produces an error signal 25 indicating the phase difference between the reference signal 21 and the divider signal 45. The error signal 25 is provided to the charge pump and loop filter 103. The charge pump converts this phase difference into positive or negative pulses depending on whether the reference clock signal phase leads or lags the divider signal phase and the loop filter integrates these pulses to generate a control voltage 27, which is provided to VCO 105. The VCO 105 produces an output signal (Pllout) 42 having a frequency which is proportional to control voltage 27, and the output signal 42 is applied to the input of the frequency divider 106. The output signal of frequency divider 106, that is, divider signal 45, is fed back to input of PFD 102.
The frequency at which the phase-locked loop operates is dependent upon the frequency of the reference clock signal 21 and the amount of division by the frequency divider 106. To change frequency of output signal 42 from VCO 105, these elements must be adjusted. Typically, the frequency of output signal 42 is divided by an integer ratio ‘N’ such that the frequency of output signal 42 is N times of the frequency of the divider signal 45. When the loop is “locked”, the control voltage 27 applied by charge pump and loop filter 103 to VCO 105 drives the phase difference between PFD 102 input signals 21 and 45 to zero, such that divider signal 45 has a frequency which is equal to the frequency of reference clock signal 21, and which is in phase with clock signal 21. Output signal 42 is then inputted into a post divider 107 to be divided by 1, 2, 3, 4 or other integer ratio ‘M’ such that the frequency of the output signal 30 is 1/M times of the frequency of VCO output signal 42.
VCO 105 is conventionally made from a ring oscillator which has a wide output frequency range, as such, it is well-suited for use in PLL circuits which lock to a wide range of desired output frequencies from the same VCO. One drawback to the use of a ring oscillator-based VCO is its relatively high output jitter. In some applications, clock jitter is required to be smaller than a particular value. To lower clock jitter, the circuit's VCO may employ another type of oscillator—such as an LC-tank oscillator—having a superior jitter characteristic, but narrower tuning range.
High-speed serial data signal transmitter/receiver circuitry may include PLL circuitry for producing a clock signal. For multi-data-rate communications protocol support, this PLL may need to operate at a wide range of frequencies that span tens of gigahertz. Post-divider 107 or other circuitry downstream from the PLL is provided for dividing the frequency of the PLL output clock signal by a dynamically selectable factor M. Selectable values of this factor may include 1 and another value such as 2 (or more), which other value is appropriate for modifying the PLL output clock signal frequency to a lower frequency that supports operation of the transmitter at another data rate (not the highest data rate) required by the multi-data-rate communication protocol.
The best high frequency PLL's that offer the best phase noise are made by using LC-tank Voltage Controlled Oscillators. If the design of the VCO is for a very high frequency it is sometimes not possible to have the VCO cover a wide frequency range, e.g., a full octave after accounting for process, temperature, and voltage variations, together with any calibration or compensation mechanisms for mitigating the effects of such variations. (An octave is a frequency range in which the highest frequency is twice the lowest frequency. If an octave is achieved, downstream dividers can be employed to extend the lower end of the frequency range without any gaps or “holes”.) Unfortunately, when the maximum frequency output of the PLL is pushed higher, achieving an octave or more of frequency range becomes challenging. Typical ranges can be 1.4-1.8.
If the VCO covers a range of less than 2, then the output signal 30 will have undesirable holes in the frequency range coverage. For instance, if the VCO covers a range of 13.33 GHz-20 GHz, then the output frequencies will be shown in table 1.
TABLE 1Post DividerVCO FrequencyClkout frequencySettingRangerange113.33 GHz-20 GHz13.33 GHz-20 GHz213.33 GHz-20 GHz 6.67 GHz-10 GHz313.33 GHz-20 GHz  4.45 GHz-6.67 GHz413.33 GHz-20 GHz3.33 GHz-5 GHz
The frequency range coverage of the VCO is 20 GHz/13.33 GHz=1.5, which is less than 2. As it can be seen from table 1, there are frequency gaps in the output frequency coverage between 10 GHz to 13.33 GHz when post divider setting is changed from 1 to 2, which means that the frequency cannot vary continuously.